The present invention relates to a delay locked loop circuit, and more particularly, to a delay locked loop circuit capable of preventing the malfunction due to the glitch of a clock.
FIG. 1 illustrates a block diagram of a conventional delay locked loop circuit having a single loop structure.
As shown in FIG. 1, the conventional delay locked loop circuit having the single loop structure may include a clock buffering block 101, a phase comparing block 103, a delaying block 105, a replica modeling block 107 and a pulse generating block 109.
The clock buffering block 101 outputs an input clock REF_CLK by buffering an external clock EXT_CLK. The clock buffering block 101 is inactivated in response to a buffer control signal BUF_EN that is enabled when the delay locked loop circuit enters a power down mode and, at this time, the input clock REF_CLK is disabled. The clock being disabled means that the clock is not toggled.
The phase comparing block 103 compares the input clock REF_CLK with a feedback clock FB_CLK outputted from the replica modeling block 107 and outputs a phase comparison signal CMP including information for a phase difference of the input clock REF_CLK and the feedback clock FB_CLK to the delaying block 105, wherein the feedback clock FB_CLK is obtained by modeling components of delaying a clock inside a semiconductor memory device.
The delaying block 105 determines a delay amount in response to the phase comparison signal CMP and outputs an internal clock CLK_OUT by delaying the input clock REF_CLK by the delay amount.
The internal clock CLK_OUT is coupled to the replica modeling block 107. If the phase of the input clock REF_CLK is consistent with that of the feedback clock FB_CLK through the above process, i.e., the delay locking, locking is achieved.
The pulse generating block 109 generates a plurality of pulse signals P_1 to P_N enabled by being synchronized with the input clock REF_CLK to control operations of the phase comparing block 103 and the delaying block 105. Namely, the phase comparing block 103 and the delaying block 105 are enabled in response to a part or all of the pulse signals P_1 to P_N. To perform the delay locking operation, a sequence of operations such as the operation of comparing the phases and the operation of delaying the input clock REF_CLK should be sequentially performed in combination with a clock. The pulse generating block 109 controls the delay locking operation to be sequentially performed.
For instance, the pulse generating block 109 generates a first pulse signal to a twelfth pulse signal, P_1 to P_12, and the phase comparing block 103 is activated in response to the second pulse signal P_2 to output the phase comparison signal CMP. The delaying block 105 is activated in response to the sixth pulse signal P_6 that is enabled after the second pulse signal P_2 is enabled, thereby delaying the input clock REF_CLK. The number or kind of the pulse signals used in the phase comparing block 103 and the delaying block 105 may be changed according to the constitution of the phase comparing block 103 and the delaying block 105. For example, in case the delaying block 105 performs a coarse delay operation and a fine delay operation, the coarse delay operation may be performed in response to the sixth pulse signal P_6 and the fine delay operation may be performed in response to the ninth pulse signal P_9. Furthermore, the number or kind of the pulse signals may be changed according to the constitution of the delay locked loop circuit. The pulse generating block 109 will be described in detail with reference to FIG. 3.
FIG. 2 illustrates a block diagram of a conventional delay locked loop circuit having a dual loop structure.
Referring to FIG. 2, the conventional delay locked loop circuit having the dual loop structure includes a clock buffering block 201, a first delay locking block 203, a second delay locking block 205, a duty rate correcting block 207 and a pulse generating block 209.
The construction and operations of the clock buffering block 201 and the pulse generating block 209 are similar to those of the clock buffering block 101 and the pulse generating block 109 in FIG. 1. Each of the first and the second delay locking blocks 203 and 205 includes a phase comparing sector, a delaying sector and a replica modeling sector like the construction of the delay locked loop circuit in FIG. 1 and is controlled by a plurality of pulse signals P_1 to P_N generated by the pulse generating block 209. Since the second delay locking block 205 inverts an input clock REF_CLK and outputs an inverted input clock in connection with a duty rate correcting operation performed in the duty rate correcting block 207, a phase of a rising edge of a first internal clock CLK_OUT1 is consistent with that of a second internal clock CLK_OUT2 and a duty rate of the first internal clock CLK_OUT1 is opposite to that of the second internal clock CLK_OUT2.
The duty rate correcting block 207 corrects duty rates of the first and second internal clocks CLK_OUT1 and CLK_OUT2 by combining the phases of the first and second internal clocks CLK_OUT1 and CLK_OUT2, thereby outputting a first and a second corrected clock CLK_CC1 and CLK_CC2. As described above, since the phase of the rising edge of the first internal clock CLK_OUT1 is consistent with that of the second internal clock CLK_OUT2, the duty rate correcting block 207 combines phases of falling edges of the first and second internal clocks CLK_OUT1 and CLK_OUT2.
FIG. 3 illustrates a detailed circuit diagram of the pulse generating block 109, 209 described in FIGS. 1 and 2.
Referring to FIG. 3, the pulse generating block 109, 209 includes a shift register 301 and a pulse control sector 315.
The shift register 301 shifts a pulse control signal START by synchronizing the pulse control signal START outputted from the pulse control sector 315 with the input clock REF_CLK, and generates the plurality of pulse signals P_1 to P_12 that are sequentially enabled. The shift register 301 includes a first to a twelfth flip-flop 303 to 314 serially connected to each other, wherein each of the first to twelfth flip-flops 303 to 314 shifts its input signal by one period of the input clock REF_CLK to output a corresponding one of the plurality of pulse signals P_1 to P_12.
The pulse control sector 315 detects a period of the first to twelfth pulse signals P_1 to P_12 and enables the pulse control signal START for every period.
The first flip-flop 303 outputs the first pulse signal P_1 that is enabled at a high level by synchronizing the pulse control signal START enabled at a high level with a rising edge of the input clock REF_CLK. The first pulse signal P_1 is inputted to the second flip-flop 304. The second flip-flop 304 generates the second pulse signal P_2 that is enabled as being delayed by one period of the input clock REF_CLK from the first pulse signal P_1. Similarly, the third to the twelfth flip-flops 305 to 314 shift output signals of their previous flip-flops by one period of the input clock REF_CLK and output the shifted signals as the third to twelfth pulse signals P_3 to P_12 that are sequentially enabled.
The pulse control sector 315 enables the pulse control signal START in response to the twelfth pulse signal P_12 and disables the pulse control signal START in response to the first pulse signal P_1. Therefore, the first flip-flop 303 enables the first pulse signal P_1 again in response to the pulse control signal START and the pulse signals P_1 to P_12 become pulse signals having a predetermined period. The pulse signals inputted to the pulse control sector 315 can be changed and the period of the first to the twelfth pulse signals can be adjusted according to the pulse signals inputted to the pulse control sector 315. For instance, if the pulse control signal START is enabled in response to the sixth pulse signal P_6, the period of the first to twelfth pulse signals P_1 to P_12 becomes shorter.
The pulse control sector 315 includes an OR gate 317, an SR latch 319 and a NOR gate 321. An output signal of the OR gate 317 receiving the twelfth pulse signal P_12 and a reset signal RESET is inputted to an input node R of the SR latch 319. The first pulse signal P_1 is inputted to an input node S of the SR latch 319. Since the first and twelfth pulse signals P_1 and P_12 are disabled at a low level before the reset signal RESET is disabled, the reset signal RESET is inputted to the OR gate 317 so as to establish an initial value of the SR latch 319 and enable the pulse control signal START in the early stage of the operation.
The SR latch 319 makes a logic level of an A node being a low level in response to the twelfth pulse signal P_12 and a logic level of the A node being a high level in response to the first pulse signal P_1. The SR latch 319 maintains the logic level of the A node at the high level while the first pulse signal P_1 and the twelfth pulse signal P_12 are disabled.
If the reset signal RESET is changed from an enabled state having a high level to a disabled state having a low level, the logic level of the A node is maintained at the low level by the SR latch 319. The pulse control signal START is enabled at a high level after the reset signal RESET is disabled at the low level by the NOR gate 321 receiving the reset signal RESET. The first pulse signal P_1 is enabled at a high level in response to the pulse control signal START that is enabled.
FIGS. 4A and 4B illustrate timing diagrams for the pulse generating block 109, 209 described in FIG. 3. FIG. 4A illustrates a timing diagram for the pulse generating block 109, 209 in a normal mode. FIG. 4B illustrates a timing diagram for the pulse generating block 109, 209 during the delay locked loop circuit coming out of a power down mode after it enters the power down mode.
Referring to FIG. 4A, if the reset signal RESET is disabled at the low level from the high level, the pulse control signal START is enabled at the high level by the pulse control sector 315. The shift register 301 is synchronized with the input clock REF_CLK in response to the pulse control signal START and generates the plurality of pulse signals P_1 to P_12 that are sequentially enabled. The pulse control sector 315 outputs the pulse control signal START that is enabled in response to the twelfth pulse signal P_12 and disabled in response to the first pulse signal P_1.
Referring to FIG. 4B, the input clock REF_CLK is disabled when the delay locked loop circuit enters the power down mode and enabled again when the delay locked loop circuit exits from the power down mode. In case the delay locked loop circuit enters the power down mode after the first pulse signal P_1 is enabled, the enabled state of the first pulse signal P_1 is maintained as the input clock REF_CLK is disabled. Then, in case the delay locked loop circuit exits from the power down mode, the glitch may occur in the input clock REF_CLK. Since the operation of the shift register 301 becomes unstable due to the glitch, the first flip-flop 303 disables the first pulse signal P_1 in response to the glitch and the second pulse signal P_2 is not enabled in case the second flip-flop 304 does not respond to the glitch. Therefore, the shift register 301 does not enable the pulse signals anymore.
After all, in the conventional delay locked loop circuit, in case a certain pulse signal is disabled by external noise or the glitch of the clock that can occur when the delay locked loop circuit exits from the power down mode, the shift register 301 does not enable the pulse signals P_1 to P_12 sequentially and thus the delay locked loop circuit operating in response to the plurality of pulse signals P_1 to P_12 may not perform its operation.